The ESD protection structure of a mainstream double diffused metal oxide semiconductor field effect transistor (DMOSFET) device having the ESD protection is achieved by manufacturing a diode on the polysilicon, the structure of which is shown in FIG. 1, and the diode is disposed in parallel between a source and a gate of the device. In order to electrically insulate the diode from other cell circuits, an insulating layer having a certain thickness should be made under the diode on the wafer during fabrication as required, therefore the area is higher than the other tube core areas. As semiconductor processes entering into a smaller linewidth era, the dielectric process of which has also developed into the relatively advanced chemical mechanical polishing (CMP) process. However, there are problems that a thicker dielectric thickness has to be set while performing the CMP process to ensure the process margin for the subsequent process due to high steps in part of areas, thereby sacrificing part of the performances of the tube core and causing the instability of the process itself, simultaneously.